This disclosure is related to the application entitled xe2x80x9cSelf-test of a Memory Device,xe2x80x9d invented by Ray Beffa, William Waller, Warren Farnworth, Leland Nevill, and Eugene Cloud, filed on Apr. 22, 1997, the contents of which are hereby incorporated by reference.
The present disclosure relates generally to the computer memory field, and more particularly, to on-chip testing of dynamic random access memory (DRAM) semiconductor chips.
A DRAM memory cell (memory bit) is a binary memory element formed with one transistor and one capacitor. A modern DRAM memory unit may contain many millions of addressable memory cells. Each cell""s capacitor holds binary information in the form of charge, and the cell""s transistor operates as a switch to introduce and control the charge stored on the capacitor.
The memory cells are organized into arrays. To access a particular memory cell when performing a read operation, the operator supplies the DRAM with the address of the cell to be accessed. The DRAM translates the address into a row address and a column address of the array the memory cell is located in, and the addressed column and row are then accessed and the charge stored on the memory cell capacitor at the intersection of the addressed column and row is sensed.
FIG. 1 is a diagram showing a memory cell array map for a 4Megxc3x974 DRAM (i.e., a DRAM with sixteen million total bits, Ser. No. 08/838,010, now U.S. Pat. No. 5,910,010 accessible in four million, four-bit units). Array maps for other size DRAMs are similar. The DRAM is divided into four quadrants, each made up of a series of rows, such as rows 104 and 106, and columns, such as column 107. The rows in quadrants one and three have addresses extending from zero to 1023, and are accessed four at a time. That is, because each row address in a quadrant is repeated four times, access to any row address drives four physical rows in the accessed quadrant. Each column in a quadrant, such as quadrant three, intersects all four active rows. The column addresses in quadrants one and three extend from zero to 2047. The addressing scheme is similar for quadrants two and four. For each bit that is eventually output by the DRAM, the active column and the active physical rows access four bits in a quadrant. Additional circuitry on the DRAM selects certain of the four accessed bits and places them on the appropriate output data pin(s). In this example, two bits are selected from the physical rows accessed in quadrant three, corresponding to output DQs 2 and 3, and two bits are selected from the physical rows accessed in quadrant one, corresponding to output DQs 1 and 4.
Before shipping a DRAM semiconductor chip, it must be tested to ensure that all the memory cells function properly. One conventional method of testing a DRAM is to have an external testing device store data in every memory cell in the DRAM, and then read out every memory cell in the DRAM. In this manner, DRAM defects can be detected by comparing the known input data to the output data. However, as DRAMs increase in capacity, accessing all the memory cells begins to take an inordinate amount of time. For example, in the case of a 4Megxc3x974 DRAM, conventional testing techniques would require four million write cycles and four million read cycles to fully test the DRAM one time.
A second conventional method decreases testing time by taking advantage of the fact that multiple bits are sensed when a row address and a column address are accessed in a quadrant. In this method, circuitry is placed on the DRAM chip, which operates on the multiple data bits sensed for each row and column address. The circuitry transmits a logic one if all the sensed data bits are a logic one, a logic zero if all the sensed data bits are a logic zero, and enters a high impedance state if the data bits are mixed, i.e., both logic ones and zeros.
To perform a DRAM test with the second conventional method, the external testing unit writes either all ones or all zeroes to the row and column addresses to be tested, and then performs a read operation on the addresses. For each address read by the testing unit, the internal DRAM test circuitry outputs a one, zero, or high impedance state, thus informing the testing unit whether any of the bits sensed are bad. By testing a plurality of data bits simultaneously, testing time is reduced.
A goal of both of the above described conventional testing techniques is to replace defective addresses when found. One way to do this is to fabricate the DRAM memory arrays with extra rows and columns of cells, which are normally not used, but which can be substituted for rows or columns of cells found to be defective. In FIG. 1, columns 108, 109 and rows 112, 113 are designated as extra rows and columns, called redundant rows and columns, respectively. For example, a 4Megxc3x974 DRAM may have eight redundant rows and four redundant columns per quadrant.
When a defective row or column is found, fuses are blown, isolating the defective row or column and mapping one of the redundant rows 112, 113 or one of the redundant columns 108, 109 to the address previously occupied by the defective row or column. In this manner, a memory array with a limited number of defective memory cells can be completely repaired. However, if there are too many defective memory cells, such that there are not enough redundant rows and columns to completely repair all of the defective memory cells, the die is considered xe2x80x9cbadxe2x80x9d and may have to be discarded.
It is important that the available supply of redundant rows and columns be allocated efficiently to repair defective memory cells. For example, assuming that X""s 110 and 111 in FIG. 1 represent defective memory cells, one could repair these two cells by substituting redundant rows 112 and 113 for rows 104 and 106, respectively, or by substituting only one of redundant columns 108 and 109 for column 107. Obviously, the second substitution is the more efficient way of repairing defective cells 110 and 111, because it repairs two defective cells with only one redundant column. Relative to repairing defective cells 110 and 111 with redundant rows 112 and 113, repairing with one of redundant columns 108 and 109 is called a xe2x80x9cpreferred-repair.xe2x80x9d A term related to preferred repairs is the so-called xe2x80x9cmust-repairxe2x80x9d. A must repair in the row direction is encountered when the number of bad bits in a row is greater than the number of available redundant column. Similarly, a must-repair in the column direction refers to the situation that occurs when the number of bad bits in a column is greater than the number of available redundant rows.
A conventional technique for finding must and preferred repairs uses the external testing device discussed above to form a map of the defective memory cells. The device then analyzes this xe2x80x9cmemory map,xe2x80x9d finds the required repairs, and implements an optimal repair scheme using redundant row and column substitution. This conventional testing and repair technique requires a sophisticated external testing unit, which spends a significant amount of time testing each DRAM. As DRAM sizes increase, the amount of required testing time proportionality increases. For high volume DRAM manufacture, testing time may become unacceptably long.
There is, therefore, a need to reduce the amount of time each DRAM is connected to a testing unit, and to reduce the amount of time an external testing unit needs to find and repair must and preferred repairs. Additionally, it is desirable to decrease the complexity and expense of external testing units.
Simple, fast, on-chip self-test circuitry quickly and efficiently finds and substitutes redundant rows and columns for rows and columns that are considered must/preferred repairs. The present invention is particularly advantageous because of its compact design, therefore it requires relatively little semiconductor area on the chip.
The advantages and purposes in accordance with this invention will be set forth in the following description and will also be obvious from the description, or may be learned by practicing the invention. The advantages and purpose of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To obtain the advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, in one embodiment, the present invention is in the form of a memory fabricated on a semiconductor chip, comprising a memory array addressable with row and column addresses; a row counter connected to supply row addresses to the memory array; and a column counter connected to supply column addresses to the memory array. Finally, control circuitry is included coupled to the row counter and the column counter, the control circuitry operating the row and column counters to access each memory element in the memory array twice, once in column-major order and once in row-major order.
In another embodiment, the present invention is a method of locating must/preferred repairs orientated in a row direction within a memory array on a semiconductor chip, comprising the steps of: sequentially accessing the memory cells in a row of the memory array; comparing a value of each of the accessed memory cells of the row with test values pre-written to the memory cells of the row; storing a running total of the number of dissimilar comparisons performed by the comparing step; and repeating the sequential accessing, comparing, and storing steps for each row in the memory array.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not restrict the invention, as claimed. dr
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIG. 1 is a diagram showing a memory cell array map for a 4Megxc3x974 DRAM;
FIG. 2 is a conceptual block diagram illustrating a DRAM with a self-test capability according to the present invention;
FIG. 3 is diagram of a nine element array;
FIGS. 4 illustrates a quadrant of a 4Megxc3x974 DRAM indexed in row-major order;
FIGS. 5 illustrates a quadrant of a 4Megxc3x974 DRAM indexed in column-major order; and
FIGS. 6A, 6B, and 7 are flow-charts illustrating the preferred operation of the present.